1. Field of the Invention
The present invention relates to the field of voltage charge pumps of integrated circuits and specifically to those used to generate reprogramming voltages for memory devices.
2. Art Background
In the field of memory devices such as erasable flash EPROMs and EEPROMs, it is essential to use a 12 V supply (Vpp) when reprogramming the memory devices. Once the command to erase, program, or verify is issued, the device internally generates the required voltages from the Vpp supply. The command register controls selection of internal reference circuitry tapped off of Vpp. An improper Vpp level causes the references to be wrong, degrading the performance of the device.
Typically, higher reprogramming voltages can be generated by pumping from a lower voltage using a charge pump, DC/DC converter, etc. Currently charge pumps are used in applications that require generation of a voltage above the power supply rail with a small current demand, e.g. EEPROMs. For flash EPROMs, however, a potential less than that required for EEPROMs but with current requirements approximately 100 to 1,000 times of EEPROMs are required (in the neighborhood of 1 to 20 mA).
Also, since this new class of charge pumps will necessarily have to be very much larger in area (i.e., much larger pump capacitors) than their EEPROM predecessors, the question of process reliability and raw wafer yield will become a factor in the manufacture of microchip with these sizes of charge pumps.
FIG. 1 illustrates a prior art single series charge pump 10. The single series charge pump 10 uses a two phase clock, CLK 100 and CLK-bar 101, applied to non-adjoining transistor-capacitor nodes. As charges are pumped from Vdd to node Vout through the pumping capacitors 121, 131, 141, 151 and the diode-connected transistors 1 1 0, 120, 130, 140, and 150, an output voltage greater than Vdd can be generated.
The prior art single series charge pump 10 still has its drawbacks. First, because the charge pump for flash EPROMs requires a much greater switching current than EEPROM, noise can be introduced into the power supplies on the chip. Such noise is intolerable and can be detrimental to the system, and additional noise suppression techniques must be implemented. Also, the charge pump produces greater output ripples at the switching frequency because all the charges are transferred to the output load at the same time. Furthermore, a single series charge pump cannot be fault-tolerant, if one capacitor shorts out, causing the charge pump to malfunction.
As will be described, the present invention will demonstrate several unique features implemented specifically for a charge pump to be tolerant to process and wear-induced defects in the charge pump capacitors, which are about 95% of the active area of the charge pump.
These unique features will also enable a charge pump to operate at a high percentage of its output current capability, e.g. more than 90% of normal capacity achievable given enough parallel charge pump segments.
These unique features will further ensure that capacitor defects will not induce bipolar-type latch-up currents in the CMOS process due to a specially designed all-NMOS clock driver output buffer with particular application for N-well CMOS process.